The multi-channel ��ֱ�� PHY IP for PCI Express? (PCIe?)5.0 and CXL includes ��ֱ�� high-speed, high-performance transceiver to meet today��s demands for higher bandwidth. The PHY meets the needs of today��s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.

Using leading-edge design, analysis, simulation, and measurement techniques, ��ֱ�� delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standards electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity, reducing both product development cycles and the need for costly field support.

��ֱ�� IP PHY IP for PCI Express 5.0 and CXL

Highlights

Products

Downloads and Documentation

Supports all required features of the PCIe? 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
x1, x2, x4, x8, x16 lane configurations with bifurcation
Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
Adaptive receiver equalizer with programmable settings
Supports lane margining at the receiver
Supports L1 substate power management
Power gating
Embedded Bit Error Rate (BER) tester and internal eye monitor
Built-in Self Test vectors, PRBS generation and checker
IEEE 1149.6 AC JTAG Boundary Scan
Supports -40��C to 125��C junction temperatures
Supports flip-chip packaging

PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2	STARs	Subscribe
Differential Buffer, TSMC N5, North/South (vertical) poly orientation	STARs	Subscribe
10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF5A x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF G2, x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF G2, x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC7FF G2, x6, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, NCS,TSMC N5 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, NCS,TSMC N5 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SF4X, x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS 10LPP x16, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS 10LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS 10LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS 10LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS 10LPP x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF4X x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF4X x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF5 x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF5 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF5 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPP x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPP x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPP x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPU x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS8LPU x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, SS SF2 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC12FFC x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC16FFC+ x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC16FFC x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N3E x1, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N3E x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N3E x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N3E x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N3P x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N3P x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N5 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY,TSMC N5 x8, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N6 x2, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation	STARs	Subscribe
PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation	STARs	Subscribe

Description:	10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc7ff_ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer Databook for TSMC 7FF (PHY Version: 2.09a) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 7FF (PHY Version: 2.09a) ( TEXT )
Download:	dwc_diffbuf_tsmc7ff_ns
Product Code:	C522-0

Description:	Differential Buffer, TSMC N5, North/South (vertical) poly orientation
Name:	dwc_diffbuf_tsmc5ff_ns
Version:	3.07a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databook DesignWare Cores Differential Buffer for TSMC 5FF (PHY Version:3.07a_d1) ( PDF \| HTML ) Release Notes DesignWare Cores Differential Buffer Release Notes for TSMC 5FF (PHY Version: 3.07a) ( TEXT )
Download:	dwc_diffbuf_tsmc5ff_ns
Product Code:	F690-0

Description:	PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc7ff_x4ns
Version:	2.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databook ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Databook (PHY Version: 2.04a) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Reference Manual (PHY Version: 2.04a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Reference Manual with Changes (PHY Version: 2.04a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Release Notes (PHY Version: 2.04a) ( TEXT )
Download:	dwc_pcie5phy_ncs_tsmc7ff_x4ns
Product Code:	G230-0

Description:	PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc7ff_x1ns
Version:	2.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP Compilation Using the LC and FC End-User Platform (32G PHY; Doc Version: 1.20a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x1 for TSMC 7FF Databook (PHY Version: 2.04a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x1 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x1 for TSMC 7FF Reference Manual (PHY Version: 2.04a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x1 for TSMC 7FF Release Notes (PHY Version: 2.04a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ncs_tsmc7ff_x1ns
Product Code:	G562-0

Description:	PCIe 5.0 PHY, NCS,TSMC N5 x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc5ff_x2ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Databooks PCIe 5.0 PCS for ��ֱ�� PHY IP PCIe 5.0 PHY x2 for TSMC 5FF/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 x2 PHY for TSMC 5FF Databook (PHY Version: 3.03a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 5FF Reference Manual (PHY Version: 3.03a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 5FF Release Notes (PHY Version: 3.03a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ncs_tsmc5ff_x2ns
Product Code:	F832-0

Description:	PCIe 5.0 PHY, NCS,TSMC N5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc5ff_x4ns
Version:	3.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks PCIe 5.0 PCS for the ��ֱ�� PHY IP PCIe 5.0 PHY x4 for TSMC 5FF/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 x4 PHY for TSMC 5FF Databook (PHY Version: 3.04a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 5FF Reference Manual (PHY Version: 3.04a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 5FF Release Notes (PHY Version: 3.04a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ncs_tsmc5ff_x4ns
Product Code:	F833-0

Description:	PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ncs_tsmc6ff_x4ns
Version:	2.06a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Databook (PHY Version: 2.06a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x4 for TSMC 6FF PHY/PCS Wrapper Databook (PCS Version: 1.58a; PHY Version 2.06a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Reference Manual (PHY Version: 2.06a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Release Notes (PHY Version: 2.06a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ncs_tsmc6ff_x4ns
Product Code:	G102-0

Description:	PCIe 5.0 PHY, SF4X, x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_sf4x_x1ns
Version:	1.03d
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY x1 for SF4X Databook (PHY Version: 1.03d_d1) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x1 for SF4X (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5.0 PHY x1 for SF4X Reference Manual (PHY Version: 1.03d) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIE 5 PHY x1 for SF4X Release Notes (PHY Version: 1.03d) ( TEXT )
Download:	dwc_pcie5phy_sf4x_x1ns
Product Code:	F470-0

Description:	PCIe 5.0 PHY, SS 10LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss10lpp_x1ns
Version:	1.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS< 1.13)) ( PDF \| HTML ) DesignWare? Cores PHY �C External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) Databooks DesignWare? Cores Multi-Protocol PCIe 5 PHY for Samsung 10LPP x1 Databook (PHY Version: 1.04a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY Databook (PCS Version: 1.46b) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY for Samsung 10LPP x1 Release Notes (PHY Version: 1.04a) ( TEXT )
Download:	dwc_pcie5phy_ss10lpp_x1ns
Product Code:	E152-0

Description:	PCIe 5.0 PHY, SS 10LPP x16, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss10lpp_x16ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie5phy_ss10lpp_x16ns
Product Code:	E156-0

Description:	PCIe 5.0 PHY, SS 10LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss10lpp_x2ns
Version:	1.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.10a (Raw PCS< 1.13)) ( PDF \| HTML ) DesignWare? Cores PHY �C External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.20) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) Databooks DesignWare? Cores Multi-Protocol PCIe 5 PHY for Samsung 10LPP x2 Databook (PHY Version: 1.04a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY Databook (PCS Version: 1.46b) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY for Samsung 10LPP x2 Release Notes (PHY Version: 1.04a) ( TEXT )
Download:	dwc_pcie5phy_ss10lpp_x2ns
Product Code:	E153-0

Description:	PCIe 5.0 PHY, SS 10LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss10lpp_x4ns
Version:	3.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY x4 for SS 10LPP Databook (PHY Version: 3.00a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5 PHY x4 for SS 10LPP PHY/PCS Wrapper Databook (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x4 for SS 10LPP Reference Manual (PHY Version: 3.00a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x4 for SS 10LPP Release Notes (PHY Version: 3.00a) ( TEXT )
Download:	dwc_pcie5phy_ss10lpp_x4ns
Product Code:	E154-0

Description:	PCIe 5.0 PHY, SS 10LPP x8, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss10lpp_x8ns
Version:	1.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie5phy_ss10lpp_x8ns
Product Code:	E155-0

Description:	PCIe 5.0 PHY, SS SF2 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_sssf2_x4ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x4 for Samsung SF2 Databook (PHY Version: 3.01a_d2) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x4 for Samsung SF2 PHY/PCS Wrapper Databook (PCS Version: 1.58a; PHY Version: 3.01a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x4 for Samsung SF2 Reference Manual (PHY Version: 3.01a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for Samsung SF2 Release Notes (PHY Version: 3.01a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_sssf2_x4ns
Product Code:	G935-0

Description:	PCIe 5.0 PHY, SS SF4X x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss4lpp_x2ns
Version:	1.03d
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5.0 PHY x2 for SS 4LPP Databook (PHY Version: 1.03d_d2) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x2 for SS 4LPP (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5.0 PHY x2 for SS 4LPP Reference Manual (PHY Version: 1.03d_d1) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5.0 PHY x2 for SS 4LPP Release Notes (PHY Version: 1.03d) ( TEXT )
Download:	dwc_pcie5phy_ss4lpp_x2ns
Product Code:	F471-0

Description:	PCIe 5.0 PHY, SS SF4X x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss4lpp_x4ns
Version:	2.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks DesignWare? Cores PCIe 5.0 PHY x4 for SS 4LPP Databook (PHY Version: 2.01a_d1) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x4 for SS 4LPP (PCS Version: 1.55a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5.0 PHY x4 for SS 4LPP Reference Manual (PHY Version: 2.01a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5.0 PHY x4 for SS 4LPP Release Notes (PHY Version: 2.01a) ( TEXT )
Download:	dwc_pcie5phy_ss4lpp_x4ns
Product Code:	F472-0

Description:	PCIe 5.0 PHY, SS SF5 x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss5lpe_x1ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook DesignWare? Cores PCIe 5 PHY x1 for SS 5LPe Databook (PHY Version: 1.02a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x1 for SS 5LPe Release Notes (PHY Version: 1.02a) ( TEXT )
Download:	dwc_pcie5phy_ss5lpe_x1ns
Product Code:	F414-0

Description:	PCIe 5.0 PHY, SS SF5 x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss5lpe_x2ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie5phy_ss5lpe_x2ns
Product Code:	F415-0

Description:	PCIe 5.0 PHY, SS SF5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss5lpe_x4ns
Version:	1.04b
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 1.50a (Raw PCS >= 1.16)) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY x4 for SS 5LPe Databook (PHY Version: 1.04b) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x4 for SS5LPE PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x4 for SS 5LPe Reference Manual (PHY Version: 1.04b) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x4 for SS 5LPe Release Notes (PHY Version: 1.04b) ( TEXT )
Download:	dwc_pcie5phy_ss5lpe_x4ns
Product Code:	F416-0

Description:	PCIe 5.0 PHY, SS SF5A x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_a00_ss5lpe_x2ns
Version:	1.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks DesignWare? Cores PCIe 5 PHY x2 for SS 5LPE Databook (PHY Version: 1.08a_d1) ( PDF \| HTML ) PCIe 5.0 PCS for DesignWare? Cores PCIe 5.0 PHY x2 for SS 5LPE PHY/PCS Wrapper Databook (PCS Version: 1.56a; PHY Version: 1.08a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x2 for SS 5LPE Reference Manual (PHY Version: 1.08a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x2 for SS 5LPE Release Notes (PHY Version: 1.08a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_a00_ss5lpe_x2ns
Product Code:	H222-0

Description:	PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_a00_ss5lpe_x4ns
Version:	1.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks DesignWare? Cores PCIe 5 PHY x4 for SS 5LPe Databook (PHY Version: 1.08a) ( PDF \| HTML ) PCIe 5.0 PCS for DesignWare? Cores PCIe 5.0 PHY x4 for SS 5LPE PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x4 for SS 5LPe Reference Manual (PHY Version: 1.08a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x4 for SS 5LPe Release Notes (PHY Version: 1.08a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_a00_ss5lpe_x4ns
Product Code:	H115-0

Description:	PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
Name:	dwc_ap_pcie5phy_sssf5a_x4ns
Version:	1.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks PCIe 5.0 PCS for ��ֱ�� PHY IP PCIe 5.0 PHY x4 for SS SF5A PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for SS SF5A Databook (PHY Version: 1.00a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x4 for SS SF5A Reference Manual (PHY Version: 1.00a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for SS SF5A Release Notes (PHY Version: 1.00a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_ap_pcie5phy_sssf5a_x4ns
Product Code:	I446-0

Description:	PCIe 5.0 PHY, SS7HPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss7hpp_x4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores 32G PHY ATE Testbench (Doc Version: 1.0) ( PDF ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) Databook DesignWare? Cores PCIe 5 PHY for Samsung LN7HPP Databook (PHY Version: 1.03a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY for Samsung LN7HPP Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	dwc_pcie5phy_ss7hpp_x4ns
Product Code:	E128-0

Description:	PCIe 5.0 PHY, SS8LPP x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpp_x1ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Databooks PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x1 for SS8LPP PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x1 for SS 8LPP Databook (PHY Version: 1.03a_d2) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x1 for SS 8LPP Reference Manual (PHY Version: 1.03a_d2) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x1 for SS 8LPP Reference Manual with Changes (PHY Version: 1.03a_d2) ( PDF ) Release Notes DesignWare? Cores PCIe 5 PHY x1 for SS 8LPP Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	dwc_pcie5phy_ss8lpp_x1ns
Product Code:	F475-0

Description:	PCIe 5.0 PHY, SS8LPP x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpp_x2ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks PCS for the DesignWare? Cores PCIe 5.0 PHY x2 for SS8LPP PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPP Databook (PHY Version: 1.03a_d2) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPP Reference Manual (PHY Version: 1.03a_d2) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPP Reference Manual with Changes (PHY Version: 1.03a_d2) ( PDF ) Release Notes DesignWare? Cores PCIe 5 PHY x2 for SS8LPP Release Notes (PHY Version: 1.03a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ss8lpp_x2ns
Product Code:	F476-0

Description:	PCIe 5.0 PHY, SS8LPP x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpp_x4ns
Version:	1.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks DesignWare? Cores PCIe 5 PHY x4 for SS8LPP PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for SS8LPP Databook (PHY Version: 1.03a_d2) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x4 for SS 8LPP Reference Manual (PHY Version: 1.03a_d2) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for SS 8LPP Reference Manual with Changes (PHY Version: 1.03a_d2) ( PDF ) Release Notes DesignWare? Cores PCIe 5 PHY x4 for SS8LPP Release Notes (PHY Version: 1.03a) ( TEXT )
Download:	dwc_pcie5phy_ss8lpp_x4ns
Product Code:	F477-0

Description:	PCIe 5.0 PHY, SS8LPU x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpu_x2ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPU Databook (PHY Version: 1.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x2 for SS 8LPU PHY/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x2 for SS 8LPU PHY/PCS Wrapper Databook with Tracked Changes (PCS Version: 1.58a) ( PDF ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPU Reference Manual (PHY Version: 1.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPU Reference Manual with Changes (PHY Version: 1.02a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x2 for SS 8LPU Release Notes (PHY Version: 1.02a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ss8lpu_x2ns
Product Code:	H728-0

Description:	PCIe 5.0 PHY, SS8LPU x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_ss8lpu_x4ns
Version:	1.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x4 for SS 8LPU Databook (PHY Version: 1.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x4 for SS 8LPUPHY/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x4 for SS 8LPU Reference Manual (PHY Version: 1.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for SS 8LPU Reference Manual with Changes (PHY Version: 1.02a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for SS 8LPU Release Notes (PHY Version: 1.02a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_ss8lpu_x4ns
Product Code:	H681-0

Description:	PCIe 5.0 PHY, TSMC N3E x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc3eff_x1ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks DesignWare? Cores PCIe 5 PHY x1 for TSMC 3EFF Databook (PHY Version: 3.01a_d1) ( PDF \| HTML ) PCIe 5.0 PCS for DesignWare? Cores PCIe 5.0 PHY x1 for TSMC 3EFF/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x1 for TSMC 3EFF Reference Manual (PHY Version: 3.01a_d1) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x1 for TSMC 3EFF Release Notes (PHY Version: 3.01a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc3eff_x1ns
Product Code:	G648-0

Description:	PCIe 5.0 PHY, TSMC N3E x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc3eff_x2ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks DesignWare? Cores PCIe 5 PHY x2 for TSMC 3EFF Databook (PHY Version: 3.01a_d2) ( PDF \| HTML ) PCIe 5.0 PCS for DesignWare? Cores PCIe 5.0 PHY x2 for TSMC 3EFF/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x2 for TSMC 3EFF Reference Manual (PHY Version: 3.01a_d2) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x2 for TSMC 3EFF Release Notes (PHY Version: 3.01a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc3eff_x2ns
Product Code:	G649-0

Description:	PCIe 5.0 PHY, TSMC N3E x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc3eff_x4ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks PCIe 5.0 PCS for DesignWare? Cores PCIe 5.0 PHY x4 for TSMC 3EFF/PCS Wrapper Databook (PCS Version: 1.57a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 3EFF Databook (PHY Version: 3.03a_d1) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 3EFF Reference Manual (PHY Version: 3.03a_d1) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x4 for TSMC 3EFF Release Notes (PHY Version: 3.03a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc3eff_x4ns
Product Code:	F836-0

Description:	PCIe 5.0 PHY, TSMC N3E x8, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc3eff_x8ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Databooks ��ֱ�� PHY IP PCIe 5 PHY x8 for TSMC 3EFF Databook (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x8 for TSMC 3EFF PHY/PCS Wrapper Databook (PCS Version: 1.57a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x8 for TSMC 3EFF Reference Manual (PHY Version: 3.03a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x8 for TSMC 3EFF Release Notes (PHY Version: 3.03a) ( TEXT )
Download:	dwc_pcie5phy_tsmc3eff_x8ns
Product Code:	H042-0

Description:	PCIe 5.0 PHY, TSMC N3P x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc3pff_x4ns
Version:	3.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 3PFF Databook (PHY Version: 3.08a_d1) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x4 for TSMC 3PFF PHY/PCS Wrapper Databook (PCS Version: 1.58a, PHY Version: 3.08a_d1) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 3PFF Reference Manual (PHY Version: 3.08a_d1) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 3PFF Reference Manual with Changes (PHY Version: 3.08a_d1) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 3PFF Release Notes (PHY Version: 3.08a) ( TEXT ) User Guide ��ֱ�� PHY IP PCIe5 PHY coreKit User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc3pff_x4ns
Product Code:	F836-0

Description:	PCIe 5.0 PHY, TSMC N3P x8, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc3pff_x8ns
Version:	3.08a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP Compilation Using the LC and FC End-User Platform (32G PHY; Doc Version: 1.20a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x8 for TSMC 3PFF Databook (PHY Version: 3.08a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x8 for TSMC 3PFF PHY/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x8 for TSMC 3PFF Reference Manual (PHY Version: 3.08a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x8 for TSMC 3PFF Release Notes (PHY Version: 3.08a) ( TEXT ) User Guides ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY coreKit User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc3pff_x8ns
Product Code:	H042-0

Description:	PCIe 5.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc4ffp_x4ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie5phy_tsmc4ffp_x4ns
Product Code:	H270-0

Description:	PCIe 5.0 PHY, TSMC N5 x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc5ff_x2ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP Compilation Using the LC and FC End-User Platform (32G PHY; Doc Version: 1.20a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 5FF Databook (PHY Version: 2.08a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x2 for TSMC 5FF PHY/PCS Wrapper Databook (PCS Version: 1.58a; PHY Version: 2.08a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 5FF Reference Manual (PHY Version: 2.08a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 5FF Release Notes (PHY Version: 2.08a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc5ff_x2ns
Product Code:	E464-0

Description:	PCIe 5.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc5ff_x4ns
Version:	2.09a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks PCIe 5.0 PCS for the ��ֱ�� PHY IP PCIe 5.0 PHY x4 for TSMC 5FF PHY/PCS Wrapper Databook (PCS Version: 1.58a; PHY Version: 2.09a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 x4 PHY for TSMC 5FF Databook (PHY Version: 2.09a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 5FF Reference Manual (PHY Version: 2.09a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 5FF Release Notes (PHY Version: 2.09a) ( TEXT )
Download:	dwc_pcie5phy_tsmc5ff_x4ns
Product Code:	E465-0

Description:	PCIe 5.0 PHY, TSMC N6 x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc6ff_x2ns
Version:	3.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP Compilation Using the LC and FC End-User Platform (32G PHY; Doc Version: 1.20a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 6FF Databook (PHY Version: 3.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x2 for TSMC 6FF PHY/PCS Wrapper Databook ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 6FF Reference Manual (PHY Version: 3.02a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x2 for TSMC 6FF Release Notes (PHY Version: 3.02a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc6ff_x2ns
Product Code:	E966-0

Description:	PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc6ff_x4ns
Version:	3.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Compilation Using the LC and FC End-User Platform (32G PHY; Doc Version: 1.10a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Databook (PHY Version: 3.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x4 for TSMC 6FF PHY/PCS Wrapper Databook ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Reference Manual (PHY Version: 3.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Reference Manual with Changes (PHY Version: 3.02a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 6FF Release Notes (PHY Version: 3.02a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc6ff_x4ns
Product Code:	E967-0

Description:	PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc6ff_x6ns
Version:	3.02a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x6 for TSMC 6FF Databook (PHY Version: 3.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x6 for TSMC 6FF PHY/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5.0 PHY x6 for TSMC 6FF Reference Manual (PHY Version: 3.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5.0 PHY x6 for TSMC 6FF Reference Manual with Changes (PHY Version: 3.02a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x6 for TSMC 6FF Release Notes (PHY Version: 3.02a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc6ff_x6ns
Product Code:	F981-0

Description:	PCIe 5.0 PHY, TSMC12FFC x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc12ffc_x2ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY x2 for TSMC 12FFC Databook (PHY Version: 3.01a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x2 for TSMC 12FFC PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x2 for TSMC 12FFC Reference Manual (PHY Version: 3.01a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x2 for TSMC 12FFC Release Notes (PHY Version: 3.01a) ( TEXT )
Download:	dwc_pcie5phy_tsmc12ffc_x2ns
Product Code:	G545-0

Description:	PCIe 5.0 PHY, TSMC12FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc12ffc_x4ns
Version:	3.01a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.00a (Raw PCS >= 1.13)) ( PDF \| HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY for TSMC 12FFC Databook (PHY Version: 3.01a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x4 Databook (PCS Version: 1.56a) ( HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x4 Databook (PCS Version: 1.56a; PHY Version: 3.01a) ( PDF ) Reference Manual DesignWare? Cores PCIe 5 PHY x4 for TSMC 12FFCReference Manual (PHY Version: 3.01a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe5 PHY for TSMC 12FFC Release Notes (PHY Version: 3.01a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_tsmc12ffc_x4ns
Product Code:	E214-0

Description:	PCIe 5.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc16ffc_x4ns
Version:	2.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP High Speed SerDes Gate-Level Simulations (Doc Version: 1.12a) ( PDF \| HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY for TSMC 16FFC Databook (PHY Version: 2.04a) ( HTML ) DesignWare? Cores PCIe 5 PHY x4 for TSMC 16FFC Databook (PHY Version: 2.04a) ( PDF ) DesignWare? Cores PCIe 5 PHY x4 for TSMC 16FFC Databook (PHY Version: 2.05a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x4 Databook (PCS Version: 1.56a; PHY Version: 2.05a) ( PDF \| HTML ) Datasheet ��ֱ�� IP PHY IP for PCI Express 5.0 and CXL ( PDF ) Reference Manuals DesignWare? Cores PCIe 5 PHY x4 for TSMC 16FFC Reference Manual (PHY Version: 2.04a) ( PDF \| HTML ) DesignWare? Cores PCIe 5 PHY x4 for TSMC 16FFC Reference Manual (PHY Version: 2.05a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe5 PHY x4 for TSMC 16FFC Release Notes (PHY Version: 2.04a) ( TEXT ) DesignWare? Cores PCIe5 PHY x4 for TSMC 16FFC Release Notes (PHY Version: 2.05a) ( TEXT )
Download:	dwc_pcie5phy_tsmc16ffc_x4ns
Product Code:	D347-0

Description:	PCIe 5.0 PHY, TSMC16FFC x8, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc16ffc_x8ns
Version:	2.05a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks DesignWare? Cores PCIe 5 PHY x8 for TSMC 16FFC Databook (PHY Version: 2.05a) ( PDF \| HTML ) PCIe 5.0 PCS for the DesignWare? Cores PCIe 5.0 PHY x8 Databook (PCS Version: 1.56a; PHY Version: 2.05a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x8 for TSMC 16FFC Reference Manual (PHY Version: 2.05a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe5 PHY x8 for TSMC 16FFC Release Notes (PHY Version: 2.05a) ( TEXT )
Download:	dwc_pcie5phy_tsmc16ffc_x8ns
Product Code:	I158-0

Description:	PCIe 5.0 PHY, TSMC16FFC+ x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc16ffcp_x4ns
Version:	2.00a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Contact Us for More Information
Download:	dwc_pcie5phy_tsmc16ffcp_x4ns
Product Code:	E539-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x1, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x1ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP Compilation Using the LC and FC End-User Platform (32G PHY; Doc Version: 1.20a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x1 Gen2 for TSMC 7FF Databook (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x1 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.58a; PHY Version: 3.03a) ( PDF \| HTML ) Reference Manual ��ֱ�� PHY IP PCIe 5 PHY x1 Gen2 for TSMC 7FF Reference Manual (PHY Version: 3.03a) ( PDF \| HTML ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x1 Gen2 for TSMC 7FF Release Notes (PHY Version: 3.03a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_g2_tsmc7ff_x1ns
Product Code:	E215-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x2, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x2ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw PCS >= 1.17)) ( PDF ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.10a (Raw>=1.17)) ( HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x2 Gen2 for TSMC 7FF Databook (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x2 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.58a; PHY Version: 3.03a) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x2 Gen2 for TSMC 7FF Reference Manual (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x2 Gen2 for TSMC 7FF Reference Manual with Changes (PHY Version: 3.03a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x2 Gen2 for TSMC 7FF Release Notes (PHY Version: 3.03a) ( TEXT ) User Guide ��ֱ�� PHY IP 32G Firmware Rate Restore Feature User Guide (Doc Version: 1.30a) ( PDF \| HTML )
Download:	dwc_pcie5phy_g2_tsmc7ff_x2ns
Product Code:	I379-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x4ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) ��ֱ�� PHY IP PCIe5 PHY ATE Testbench Application Note (Doc Version: 2.00a (Raw PCS >= 1.13)) ( PDF \| HTML ) ��ֱ�� PHY IP SerDes PHY Temperature Sensor Procedure (Doc Version: 1.10a) ( PDF \| HTML ) Databooks PCIe 5 PHY PCS for the DesignWare? Cores PCIe 5 PHY Gen2 x4 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.56a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Databook (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x4 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.57a) ( PDF \| HTML ) Reference Manuals DesignWare? Cores PCIe 5 PHY x4 Gen2 for TSMC 7FF Reference Manual (PHY Version: 3.02a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Reference Manual (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Reference Manual with Change (PHY Version: 3.03a) ( PDF ) Release Notes DesignWare? Cores PCIe 5 PHY x4 Gen2 for TSMC 7FF Release Notes (PHY Version: 3.02a) ( TEXT ) ��ֱ�� PHY IP PCIe 5 PHY x4 for TSMC 7FF Release Notes (PHY Version: 3.03a) ( TEXT )
Download:	dwc_pcie5phy_g2_tsmc7ff_x4ns
Product Code:	F457-0

Description:	PCIe 5.0 PHY, TSMC7FF G2, x6, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_g2_tsmc7ff_x6ns
Version:	3.03a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G PHY IP Integration Review Checklist Application Notes (Doc Version: 1.50a) ( PDF \| HTML ) ��ֱ�� PHY IP 32G SRAM Adaptation Recording Application Notes (Doc Version: 1.30a) ( PDF \| HTML ) ��ֱ�� PHY IP External ROM and External SRAM Interfaces and Firmware Loading Application Note (Doc Version: 1.30a Raw PCS >= 1.14)) ( PDF \| HTML ) ��ֱ�� PHY IP High-Speed SerDes 32G PHY Gate-Level Simulations (Doc Version: 1.40a ( PDF \| HTML ) Databooks ��ֱ�� PHY IP PCIe 5 PHY x6 for TSMC 7FF Databook (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCS for the PCIe 5.0 PHY x6 for TSMC 7FF PHY/PCS Wrapper Databook (PCS Version: 1.58a) ( PDF \| HTML ) Reference Manuals ��ֱ�� PHY IP PCIe 5 PHY x6 for TSMC 7FF Reference Manual (PHY Version: 3.03a) ( PDF \| HTML ) ��ֱ�� PHY IP PCIe 5 PHY x6 for TSMC 7FF Reference Manual with Changes (PHY Version: 3.03a) ( PDF ) Release Notes ��ֱ�� PHY IP PCIe 5 PHY x6 for TSMC 7FF Release Notes (PHY Version: 3.03a) ( TEXT )
Download:	dwc_pcie5phy_g2_tsmc7ff_x6ns
Product Code:	H050-0

Description:	PCIe 5.0 PHY,TSMC N5 x8, North/South (vertical) poly orientation
Name:	dwc_pcie5phy_tsmc5ff_x8ns
Version:	2.04a
ECCN:	5E991/NLR
STARs:	Open and/or Closed STARs
myDesignWare:	Subscribe for Notifications
Product Type:	DesignWare Cores
Documentation:	Show Documents... Hide Documents... Application Notes DesignWare? Cores Compilation Using the LC and FC End-User Platform (Doc Version: 1.00a) ( PDF \| HTML ) SerDes PCB and Packaging Design Guide (Doc Version: 2.70a) ( PDF \| HTML ) Databook DesignWare? Cores PCIe 5 x8 PHY for TSMC 5FF Databook (PHY Version: 2.04a) ( PDF \| HTML ) Reference Manual DesignWare? Cores PCIe 5 PHY x8 for TSMC 5FF Reference Manual (PHY Version: 2.04a) ( PDF \| HTML ) Release Notes DesignWare? Cores PCIe 5 PHY x8 for TSMC 5FF Release Notes (PHY Version: 2.04a) ( TEXT )
Download:	dwc_pcie5phy_tsmc5ff_x8ns
Product Code:	G936-0