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As RISC-V adoption continues to accelerate, companies need more than just processor IP and point tools: companies adopting RISC-V need solutions.? Companies need to be able to verify RISC-V designs, whether the processor design is developed from scratch, from an open source design or by adding custom instructions to existing processor IP.? Companies need to be able to explore, analyze and optimize architectures including the individual processor, processing subsystem, and SoC.? And companies need to be able to develop software for these RISC-V processors and SoCs.? ½ðÁ«Ö±²¥ has solutions to support the full scope of a RISC-V project, including RISC-V processor IP from a vendor with more than 25 years of experience.? Couple the silicon-proven tools and methodologies with the IP and engineering services, and ½ðÁ«Ö±²¥ provides RISC-V ½ðÁ«Ö±²¥.??

Generative AI has become pervasive, enhancing the capabilities of the devices we use for inspiration, ideas, and important decision-making in our daily lives. To enable AI, large volumes of data must be processed at a fast rate, driving the industry towards multi-die designs and the adoption of high-bandwidth, low-latency interfaces such as UCIe, LPDDR, UFS, and MIPI CSI. These interfaces must not only provide real-time connectivity but also meet system-level requirements for power, performance, and area efficiency. In this paper, we will explore the motivation behind the transition to multi-die designs and examine how die-to-die, memory, storage, and MIPI interfaces interoperate to support large-scale AI-enabled systems. Additionally, we will delve into various use cases of multi-die designs in edge AI applications.

Industry consolidation and cost streamlining has eliminated many proprietary processor architectures and channeled alignment to standardized instruction set architectures (ISAs) such as RISC-V. As Moore¡¯s law slows, design teams seek different ways to deliver unique solutions for these applications while maintaining power, performance, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools, and software ecosystem, but look to extend the architecture to meet their product¡¯s unique needs. This discussion will explore how ½ðÁ«Ö±²¥¡¯ highly extensible ARC-V processor implementations can enable designers to meet their unique application requirements and provide SoC differentiation.

Test coverage is an increasingly complex Design for Test (DFT) challenge. Until recently, DFT is implemented at late stage of the design process, with limited options to impact RTL decision-making. Evolving Safety applications have imposed higher requirements on both RTL design and test coverage as high as 99%. Per ISO26262 requirements, safety mechanisms, such as safety error code, need to be used during RTL design. The large AND/OR gate dominant structural logic is instantiated as part of safety error code. Such logic 0 or 1 dominant structure is not well interpreted by ATPG engines. The path sensitization requires huge amount of care bits within patterns, lowering ATPG efficiency, Test Point Insertion effectiveness and increasing pattern counts. Moreover, large number of inputs lead to random resistance (RR) logic and limit the test coverage of an IP subsystem to less than 95%. It hinders the overall SoC coverage per AEC-100 requirement of a safety chip. ATPG pattern generation efforts can be reduced exponentially by proper assessment of the underline conditions and addressing through RTL recoding. RTL recoding can significantly improve test efficiency and logic overhead by addressing the root cause through logic splitting and other strategies. This presentation includes case studies that aim to illustrate recoding methods for improving test coverage of RR logic from 94% to 99.92%, and other scenarios of interest within actual interface IPs examples.